HD6432345 Datasheet, PDF (736/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Table A.5 Number of Cycles in Instruction Execution (cont)
Instruction Mnemonic
LDM
LDM.L @SP+,
(ERn-ERn+1)
LDM.L @SP+,
(ERn-ERn+2)
LDM.L @SP+,
(ERn-ERn+3)
LDMAC
LDMAC ERs,MACH
LDMAC ERs,MACL
MAC
MAC @ERn+,@ERm+
MOV
MOV.B #xx:8,Rd
MOV.B Rs,Rd
MOV.B @ERs,Rd
MOV.B @(d:16,ERs),Rd
MOV.B @(d:32,ERs),Rd
MOV.B @ERs+,Rd
MOV.B @aa:8,Rd
MOV.B @aa:16,Rd
MOV.B @aa:32,Rd
MOV.B Rs,@ERd
MOV.B Rs,@(d:16,ERd)
MOV.B Rs,@(d:32,ERd)
MOV.B Rs,@-ERd
MOV.B Rs,@aa:8
MOV.B Rs,@aa:16
MOV.B Rs,@aa:32
MOV.W #xx:16,Rd
MOV.W Rs,Rd
MOV.W @ERs,Rd
MOV.W @(d:16,ERs),Rd
MOV.W @(d:32,ERs),Rd
MOV.W @ERs+,Rd
MOV.W @aa:16,Rd
MOV.W @aa:32,Rd
MOV.W Rs,@ERd
Branch
Byte Word
Instruction Address Stack
Data Data Internal
Fetch
Read
Operation Access Access Operation
I
J
K
L
M
N
2
4
1
2
6
1
2
8
1
Cannot be used in the H8S/2345 Series
Cannot be used in the H8S/2345 Series
1
1
1
1
2
1
4
1
1
1
1
1
1
2
1
3
1
1
1
2
1
4
1
1
1
1
1
1
2
1
3
1
2
1
1
1
2
1
4
1
1
1
1
2
1
3
1
1
1
727