HD6432345 Datasheet, PDF (595/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

FLER bit setting conditions are as follows:
• When flash memory is read during programming/erasing (including a vector read or instruction
fetch)
• Immediately after exception handling (excluding a reset) during programming/erasing
• When a SLEEP instruction (including software standby) is executed during
programming/erasing
• When the CPU loses the bus during programming/erasing
Error protection is released only by a reset and in hardware standby mode.
Figure 17.23 shows the flash memory state transition diagram.
Memory
read verify mode
P = 1 or
E=1
RD VF PR ER FLER = 0
RES = 0 or STBY = 0
or software standby
P = 0 and
E=0
Reset release and
hardware standby release
and software standby release
Normal operating mode
Program mode
Erase mode
RD VF PR ER FLER = 0
RES = 0 or STBY = 0
Reset or hardware standby
(hardware protection)
RD VF PR ER FLER = 0
Error
occurrence
Error occurrence
(software standby)
RES = 0 or
STBY = 0
RES = 0 or
STBY = 0
FLMCR1, FLMCR2,
EBR1, EBR2
initialization state
Error protection mode
Software
standby mode
Error protection mode
(software standby)
RD VF PR ER FLER = 1
Software standby
mode release
RD VF PR ER FLER = 1
FLMCR1, FLMCR2 (except FLER
bit), EBR1, EBR2 initialization state
Legend:
RD: Memory read possible
VF: Verify-read possible
PR: Programming possible
ER: Erasing possible
RD: Memory read not possible
VF: Verify-read not possible
PR: Programming not possible
ER: Erasing not possible
Figure 17.23 Flash Memory State Transitions
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