HD6432345 Datasheet, PDF (523/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Group
Selection
CH2
0
1
Channel Selection
CH1
CH2
0
0
1
1
0
1
0
0
1
1
0
1
Single Mode
AN0 (Initial value)
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Description
Scan Mode
AN0
AN0, AN1
AN0 to AN2
AN0 to AN3
AN4
AN4, AN5
AN4 to AN6
AN4 to AN7
14.2.3 A/D Control Register (ADCR)
Bit
:
7
6
5
4
3
2
1
0
TRGS1 TRGS0 —
—
—
—
—
—
Initial value :
0
0
1
1
1
1
1
1
R/W
: R/W
R/W
—
—
R/W
—
—
—
ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D
conversion operations.
ADCR is initialized to H'3F by a reset, and in standby mode or module stop mode.
Bits 7 and 6—Timer Trigger Select 1 and 0 (TRGS1, TRGS0): Select enabling or disabling of
the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0 while conversion
is stopped.
Bit 7
TRGS1
0
1
Bit 6
TRGS0
0
1
0
1
Description
A/D conversion start by external trigger is disabled
(Initial value)
A/D conversion start by external trigger (TPU) is enabled
A/D conversion start by external trigger (8-bit timer) is enabled
A/D conversion start by external trigger pin (ADTRG) is enabled
Bits 5 to 0—Reserved: These bits are reserved; write as 1 in a write.
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