HD6432345 Datasheet, PDF (902/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Appendix E Timing of Transition to and Recovery from
Hardware Standby Mode
Timing of Transition to Hardware Standby Mode
(1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low at
least 10 states before the STBY signal goes low, as shown below. RES must remain low until
STBY signal goes low (delay from STBY low to RES high: 0 ns or more).
STBY
RES
t₁≥10t_cyc
t₂≥0ns
Figure E.1 Timing of Transition to Hardware Standby Mode
(2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do
not need to be retained, RES does not have to be driven low as in (1).
Timing of Recovery from Hardware Standby Mode
Drive the RES signal low and the NMI signal high approximately 100 ns or more before STBY
goes high to execute a power-on reset.
STBY
RES
t≥100ns
t_OSC
t_NMIRH
NMI
Figure E.2 Timing of Recovery from Hardware Standby Mode
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