HD6432345 Datasheet, PDF (164/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Table 6.3 Bus Specifications for Each Area (Basic Bus Interface)
ABWCR ASTCR
ABWn
0
ASTn
0
1
1
0
1
WCRH, WCRL
Wn1
—
0
1
—
0
1
Wn0
—
0
1
0
1
—
0
1
0
1
Bus Specifications (Basic Bus Interface)
Bus Width
Program Wait
Access States States
16
2
0
3
0
1
2
3
8
2
0
3
0
1
2
3
6.3.3 Memory Interfaces
The H8S/2345 Series memory interfaces comprise a basic bus interface that allows direct
connection of ROM, SRAM, and so on, and a burst ROM interface (for area 0 only) that allows
direct connection of burst ROM.
An area for which the basic bus interface is designated functions as normal space, and an area for
which the burst ROM interface is designated functions as burst ROM space.
6.3.4 Advanced Mode
The initial state of each area is basic bus interface, 3-state access space. The initial bus width is
selected according to the operating mode. The bus specifications described here cover basic items
only, and the sections on each memory interface (6.4 and 6.5) should be referred to for further
details.
Area 0: Area 0 includes on-chip ROM, and in ROM-disabled expansion mode, all of area 0 is
external space. In ROM-enabled expansion mode, the space excluding on-chip ROM is external
space.
When area 0 external space is accessed, the CS0 signal can be output.
Either basic bus interface or burst ROM interface can be selected for area 0.
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