HD6432345 Datasheet, PDF (619/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Programming and
Wait time: x erase possible
Programming
and
erase Wait
Wait time: x possible time: x
Programming and
erase possible
Programming
and
Wait
erase
time: x possible
φ
V_CC
FWE
t_OSC1
t_MDS
Min 0 µs
t_MDS^*2
MD₂ to MD₀
RES
SWE bit
t_MDS
SWE set
t_RESW
SWE clear
Mode switching * ¹ Boot mode Mode
User
switching * ¹ mode
User program mode
User
mode
User
program
mode
Flash memory access disabled period
(x: Wait time after SWE setting) ^*3
Flash memory reprogammable period
(Flash memory program execution and data read, other than verify, are disabled.)
Notes: 1. In transition to the boot mode and transition from the boot mode to another mode, mode switching via RES
input is necessary.
During this switching period (period during which a low level is input to the RES pin), the state of the address
dual port and bus control output signals (AS, RD, HUR, LWR) changes.
Therefore, do not use these pins as output signals during this switching period.
2. When making a transition from the boot mode to another mode, the mode programming setup time t_MDS
relative to the RES clear timing is necessary.
3. See section 20.1.6 Flash Memory Characteristics.
Figure 17.38 Mode Transition Timing
(Example: Boot Mode → User Mode ↔ User Program Mode
607