HD6432345 Datasheet, PDF (200/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Bit 7
SWDTE
0
1
Description
DTC software activation is disabled
(Initial value)
[Clearing condition]
When the DISEL bit is 0 and the specified number of transfers have not ended
DTC software activation is enabled
[Holding conditions]
• When the DISEL bit is 1 and data transfer has ended
• When the specified number of transfers have ended
• During data transfer due to software activation
Bits 6 to 0—DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits
specify a vector number for DTC software activation.
The vector address is expressed as H'0400 + ((vector number) << 1). <<1 indicates a one-bit left-
shift. For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420.
7.2.9
Bit
Module Stop Control Register (MSTPCR)
MSTPCRH
MSTPCRL
: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R/W
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR is a 16-bit readable/writable register that performs module stop mode control.
When the MSTP14 bit in MSTPCR is set to 1, the DTC operation stops at the end of the bus cycle
and a transition is made to module stop mode. However, 1 cannot be written in the MSTP14 bit
while the DTC is operating. For details, see section 19.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 14—Module Stop (MSTP14): Specifies the DTC module stop mode.
Bit 14
MSTP14
0
1
Description
DTC module stop mode cleared
DTC module stop mode set
(Initial value)
182