HD6432345 Datasheet, PDF (548/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

16.2 Register Descriptions
16.2.1 System Control Register (SYSCR)
Bit
:
7
—
Initial value :
0
R/W
: R/W
6
5
4
3
2
— INTM1 INTM0 NMIEG —
0
0
0
0
0
R/W R/W R/W R/W R/W
1
0
— RAME
0
1
R/W R/W
The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in
SYSCR, see section 3.2.2, System Control Register (SYSCR).
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
Bit 0
RAME
0
1
Description
On-chip RAM is disabled
On-chip RAM is enabled
(Initial value)
16.3 Operation
When the RAME bit is set to 1, accesses to addresses H'FFEC00 to H'FFFBFF (in the case of the
H8S/2345 and H8S/2344) or addresses H'FFF400 to H'FFFBFF (in the case of the H8S/2343,
H8S/2341, and H8S/2340) are directed to the on-chip RAM. When the RAME bit is cleared to 0,
the off-chip address space is accessed.
Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to
and read in byte or word units. Each type of access can be performed in one state.
Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start
at an even address.
16.4 Usage Note
DTC register information can be located in addresses H'FFF800 to H'FFFBFF. When the DTC is
used, the RAME bit must not be cleared to 0.
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