HD6432345 Datasheet, PDF (594/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Table 17.17 Software Protection
Item
Description
SWE bit
protection
• Clearing the SWE bit to 0 in FLMCR1 sets
the program/erase-protected state for all
blocks.
(Execute in on-chip RAM or external
memory.)
Block
specification
protection
• Erase protection can be set for individual
blocks by settings in erase block registers
1 and 2 (EBR1, EBR2).
However, write protection is disabled.
• Setting EBR1 and EBR2 to H'00 places all
blocks in the erase-protected state.
Emulation
protection
• Setting the RAMS bit to 1 in the RAM
emulation register (RAMER) places all
blocks in the program/erase-protected
state.
Note: * Program verify and erase verify modes.
Functions
Program Erase Verify*
No
No
No
—
No
Yes
No
No
Yes
17.10.3 Error Protection
In error protection, an error is detected when MCU runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in
FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2
settings are retained, but program mode or erase mode is aborted at the point at which the error
occurred. When the FLER bit is set to 1, it is not possible to re-enter the program mode or erase
mode by resetting the P and E bits of FLMCR1. However, setting of the PV and EV bits of
FLMCR1 is enabled, and a transition can be made to verify mode.
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