HD6432345 Datasheet, PDF (18/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

17.10.2 Software Protection .............................................................................................. 581
17.10.3 Error Protection .................................................................................................... 582
17.11 Flash Memory Emulation in RAM..................................................................................... 585
17.11.1 Emulation in RAM ............................................................................................... 585
17.11.2 RAM Overlap ....................................................................................................... 586
17.12 Interrupt Handling when Programming/Erasing Flash Memory........................................ 587
17.13 Flash Memory Writer Mode............................................................................................... 588
17.13.1 Writer Mode Setting ............................................................................................. 588
17.13.2 Socket Adapters and Memory Map...................................................................... 589
17.13.3 Writer Mode Operation ........................................................................................ 590
17.13.4 Memory Read Mode ............................................................................................. 592
17.13.5 Auto-Program Mode............................................................................................. 596
17.13.6 Auto-Erase Mode.................................................................................................. 598
17.13.7 Status Read Mode ................................................................................................. 599
17.13.8 Status Polling........................................................................................................ 601
17.13.9 Writer Mode Transition Time .............................................................................. 602
17.13.10 Notes On Memory Programming ....................................................................... 602
17.14 Flash Memory Programming and Erasing Precautions...................................................... 603
Section 18 Clock Pulse Generator .................................................................................. 609
18.1 Overview............................................................................................................................ 609
18.1.1 Block Diagram...................................................................................................... 609
18.1.2 Register Configuration ......................................................................................... 609
18.2 Register Descriptions......................................................................................................... 610
18.2.1 System Clock Control Register (SCKCR)............................................................ 610
18.3 Oscillator............................................................................................................................ 611
18.3.1 Connecting a Crystal Resonator ........................................................................... 611
18.3.2 External Clock Input ............................................................................................ 613
18.4 Duty Adjustment Circuit.................................................................................................... 615
18.5 Medium-Speed Clock Divider........................................................................................... 615
18.6 Bus Master Clock Selection Circuit .................................................................................. 615
Section 19 Power-Down Modes ...................................................................................... 617
19.1 Overview .............................................................................................................................. 617
19.1.1 Register Configuration............................................................................................ 618
19.2 Register Descriptions............................................................................................................ 619
19.2.1 Standby Control Register (SBYCR)....................................................................... 619
19.2.2 System Clock Control Register (SCKCR).............................................................. 620
19.2.3 Module Stop Control Register (MSTPCR) ............................................................ 621
19.3 Medium-Speed Mode ........................................................................................................... 622
19.4 Sleep Mode........................................................................................................................... 623
19.5 Module Stop Mode ............................................................................................................... 623
19.5.1 Module Stop Mode ................................................................................................. 623
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