HD6432345 Datasheet, PDF (21/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Section 1 Overview
1.1 Overview
The H8S/2345 Series is a series of microcomputers (MCUs: microcomputer units), built around
the H8S/2000 CPU, employing Hitachi's proprietary architecture, and equipped with peripheral
functions on-chip.
The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general
registers and a concise, optimized instruction set designed for high-speed operation, and can
address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300
and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300,
H8/300L, or H8/300H Series.
On-chip peripheral functions required for system configuration include data transfer controller
(DTC) bus masters, ROM and RAM memory, a16-bit timer-pulse unit (TPU), 8-bit timer,
watchdog timer (WDT), serial communication interface (SCI), A/D converter, D/A converter, and
I/O ports.
The on-chip ROM*¹ is either single power supply flash memory (F-ZTAT™*²), PROM
(ZTAT™*²), or mask ROM, with a capacity of 128, 96, 64, or 32 kbytes. ROM is connected to the
CPU via a 16-bit data bus, enabling both byte and word data to be accessed in one state.
Instruction fetching has been speeded up, and processing speed increased.
Seven operating modes, modes 1 to 7, are provided, and there is a choice of address space and
single-chip mode or external expansion mode.
The features of the H8S/2345 Series are shown in Table 1.1.
Notes: 1. The H8S/2345, H8S/2344, H8S/2343, and H8S/2341 have on-chip ROM. The
H8S/2340 does not have on-chip ROM.
2. F-ZTAT™ is a trademark of Hitachi, Ltd.
ZTAT is a trademark of Hitachi, Ltd.
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