HD6432345 Datasheet, PDF (237/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Port 2 Data Direction Register (P2DDR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
P2DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 2. P2DDR cannot be read; if it is, an undefined value will be read.
Setting a P2DDR bit to 1 makes the corresponding port 2 pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
P2DDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state after a manual reset, and in software standby mode. As the TPU and 8-bit timer are
initialized by a manual reset, the pin states are determined by the P2DDR and P2DR
specifications.
Port 2 Data Register (P2DR)
Bit
:
7
6
5
4
3
2
1
0
P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR
Initial value :
0
0
0
0
0
0
0
0
R/W
: R/W
R/W R/W
R/W R/W R/W
R/W R/W
P2DR is an 8-bit readable/writable register that stores output data for the port 2 pins (P2₇ to P2₀).
P2DR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior
state after a manual reset, and in software standby mode.
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