HD6432345 Datasheet, PDF (404/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

10.6 Usage Notes
Application programmers should note that the following kinds of contention can occur in the 8-bit
timer.
10.6.1 Contention between TCNT Write and Clear
If a timer counter clock pulse is generated during the T₂ state of a TCNT write cycle, the clear
takes priority, so that the counter is cleared and the write is not performed.
Figure 10.10 shows this operation.
ø
Address
TCNT write cycle by CPU
T₁
T₂
TCNT address
Internal write signal
Counter clear signal
TCNT
N
H'00
Figure 10.10 Contention between TCNT Write and Clear
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