HD6432345 Datasheet, PDF (582/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Start
Set pins to boot mode
and execute reset-start
Host transfers data (H'00)
continuously at prescribed bit rate
H8S/2345 measures low period
of H'00 data transmitted by host
H8S/2345 calculates bit rate and
sets value in bit rate register
After bit rate adjustment, H8S/2345
transmits one H'00 data byte to
host to indicate end of adjustment
Host confirms normal reception
of bit rate adjustment end
indication (H'00), and transmits
one H'55 data byte
After receiving H'55,
H8S/2345 transmits one H'AA
data byte to host
Host transmits number
of programming control program
bytes (N), upper byte followed
by lower byte
H8S/2345 transmits received
number of bytes to host as verify
data (echo-back)
n=1
Host transmits programming control
program sequentially in byte units
H8S/2345 transmits received
programming control program to
host as verify data (echo-back)
Transfer received programming
control program to on-chip RAM
n = N?
No
Yes
End of transmission
Check flash memory data, and
if data has already been written,
erase all blocks
After confirming that all flash
memory data has been erased,
H8S/2345 transmits one H'AA data
byte to host
Execute programming control
program transferred to on-chip RAM
n+1→n
Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is
transmitted as an erase error, and the erase operation and subsequent operations
are halted.
Figure 17.16 Boot Mode Execution Procedure
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