HD6432345 Datasheet, PDF (115/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

4.2.3 Reset Sequence
The H8S/2345 Series enters the reset state when the RES pin goes low.
To ensure that the H8S/2345 Series is reset, hold the RES pin low for at least 20 ms at power-up.
To reset the H8S/2345 Series during operation, hold the RES pin low for at least 20 states.
When the RES pin goes high after being held low for the necessary time, the H8S/2345 Series
starts reset exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip supporting modules are
initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR.
2. The reset exception handling vector address is read and transferred to the PC, and program
execution starts from the address indicated by the PC.
Figures 4.2 and 4.3 show examples of the reset sequence.
Vector Internal Prefetch of first program
fetch processing instruction
ø
RES
Internal
address bus
Internal read
signal
Internal write
signal
(1)
(3)
High
Internal data
bus
(2)
(4)
(1) Reset exception handling vector address ((1) = H'0000)
(2) Start address (contents of reset exception handling vector address)
(3) Start address ((3) = (2))
(4) First program instruction
Figure 4.2 Reset Sequence (Modes 2 and 3)
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