HD6432345 Datasheet, PDF (772/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

TCR3—Timer Control Register 3
H'FE80
TPU3
Bit
:
Initial value :
Read/Write :
7
CCLR2
0
R/W
6
5
CCLR1 CCLR0
0
0
R/W R/W
4
3
CKEG1 CKEG0
0
0
R/W R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
0
TPSC0
0
R/W
Timer Prescaler
0 0 0 Internal clock: counts on ø/1
1 Internal clock: counts on ø/4
1 0 Internal clock: counts on ø/16
1 Internal clock: counts on ø/64
1 0 0 External clock: counts on TCLKA pin input
1 Internal clock: counts on ø/1024
1 0 Internal clock: counts on ø/256
1 Internal clock: counts on ø/4096
Clock Edge
0 0 Count at rising edge
1 Count at falling edge
Counter Clear
1 — Count at both edges
0 0 0 TCNT clearing disabled
1 TCNT cleared by TGRA compare match/input capture
1 0 TCNT cleared by TGRB compare match/input capture
1 _{TCNT cleared by counter clearing for another channel}
performing synchronous clearing/synchronous operation *1
1 0 0 TCNT clearing disabled
1 TCNT cleared by TGRC compare match/input capture *2
1 0 TCNT cleared by TGRD compare match/input capture *2
1 _{TCNT cleared by counter clearing for another channel}
performing synchronous clearing/synchronous operation *1
Notes: 1. Synchronous operation setting is performed by setting the SYNC
bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not
cleared because the buffer register setting has priority, and
compare match/input capture does not occur.
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