HD6432345 Datasheet, PDF (152/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

6.1.3 Pin Configuration
Table 6.1 summarizes the pins of the bus controller.
Table 6.1 Bus Controller Pins
Name
Address strobe
Symbol
AS
Read
RD
High write
HWR
Low write
LWR
Chip select 0 to 3
Wait
CS0 to
CS3
WAIT
Bus request
Bus request
acknowledge
BREQ
BACK
I/O
Output
Output
Output
Output
Output
Function
Strobe signal indicating that address output on address
bus is enabled.
Strobe signal indicating that external space is being
read.
Strobe signal indicating that external space is to be
written, and upper half (D₁₅ to D₈) of data bus is enabled.
Strobe signal indicating that external space is to be
written, and lower half (D₇ to D₀) of data bus is enabled.
Strobe signal indicating that areas 0 to 3 are selected.
Input
Input
Output
Wait request signal when accessing external 3-state
access space.
Request signal that releases bus to external device.
Acknowledge signal indicating that bus has been
released.
6.1.4 Register Configuration
Table 6.2 summarizes the registers of the bus controller.
Table 6.2 Bus Controller Registers
Name
Abbreviation R/W
Bus width control register
ABWCR
R/W
Access state control register ASTCR
R/W
Wait control register H
WCRH
R/W
Wait control register L
WCRL
R/W
Bus control register H
BCRH
R/W
Bus control register L
BCRL
R/W
Notes: 1. Lower 16 bits of the address.
2. Determined by the MCU operating mode.
Initial Value
Power-On
Reset
Manual
Reset
H'FF/H'00*² Retained
H'FF
Retained
H'FF
Retained
H'FF
Retained
H'D0
Retained
H'3C
Retained
Address*¹
H'FED0
H'FED1
H'FED2
H'FED3
H'FED4
H'FED5
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