HD6432345 Datasheet, PDF (263/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Port B MOS Pull-Up Control Register (PBPCR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PBPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port B on an individual bit basis.
When a PBDDR bit is cleared to 0 (input port setting) in mode 2, 3, 6, or 7*, setting the
corresponding PBPCR bit to 1 turns on the MOS input pull-up for the corresponding pin.
PBPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state after a manual reset, and in software standby mode.
Note: * Modes 1 to 3 are not available on the F-ZTAT version.
Modes 2, 3, 6, and 7 are not available on the ROMless version.
8.7.3 Pin Functions
Modes 1, 4, and 5*: In modes 1, 4, and 5*, port B pins are automatically designated as address
outputs.
Port B pin functions in modes 1, 4, and 5 are shown in figure 8.10.
Port B
A₁₅ (output)
A₁₄ (output)
A₁₃ (output)
A₁₂ (output)
A₁₁ (output)
A₁₀ (output)
A₉ (output)
A₈ (output)
Figure 8.10 Port B Pin Functions (Modes 1, 4, and 5)*
Note: * Modes 1 to 3 are not available on the F-ZTAT version.
Modes 2, 3, 6, and 7 are not available on the ROMless version.
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