HD6432345 Datasheet, PDF (852/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

TIOR0H—Timer I/O Control Register 0H
H'FFD2
TPU0
Bit
:
Initial value :
Read/Write :
7
IOB3
0
R/W
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
IOA3
0
R/W
2
IOA2
0
R/W
1
IOA1
0
R/W
0
IOA0
0
R/W
TGR0A I/O Control
0 0 0 0 TGR0A Output disabled
1
is output
compare
Initial output is
1 0 ^{register 0 output}
0 output at compare match
1 output at compare match
1
Toggle output at compare match
100
Output disabled
1
10
Initial output is
1 output
0 output at compare match
1 output at compare match
1
Toggle output at compare match
1 0 0 0 TGR0A _{Capture input}
is input
1 _capture
source is
TIOCA0 pin
1 * ^register
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
TGR0B I/O Control
0 0 0 0 TGR0B Output disabled
is output
1 _compare Initial output is
1 0 ^{register 0 output}
1**
Capture input Input capture at TCNT1 count-up/
source is channel count-down
1/count clock
* : Don’t care
0 output at compare match
1 output at compare match
1
Toggle output at compare match
100
Output disabled
1
10
Initial output is
0 output
0 output at compare match
1 output at compare match
1
Toggle output at compare match
1 0 0 0 TGR0B Capture input
1
is input source is
compare TIOCB0 pin
1 * ^register
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
1**
Capture input Input capture at TCNT1 count-up/
source is channel count-down*¹
1/count clock
* : Don’t care
Note: *1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000, and ø/1 is used as the TCNT1 count clock, this setting is invalid and
input capture is not generated.
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