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HD6432345 Datasheet, PDF (175/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual
16-Bit 3-State Access Space: Figures 6.11 to 6.13 show bus timings for a 16-bit 3-state access
space. When a 16-bit access space is accessed , the upper half (D15 to D8) of the data bus is used
for the even address, and the lower half (D7 to D0) for the odd address.
Wait states can be inserted.
Bus cycle
T1
T2
T3
ø
Address bus
CSn
AS
RD
Read D15 to D8
Valid
D7 to D0
Invalid
HWR
Write
LWR
D15 to D8
High
Valid
D7 to D0
High impedance
Note: n = 0 to 3
Figure 6.11 Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access)
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