HD6432345 Datasheet, PDF (807/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

SCKCR—System Clock Control Register
Bit
:
7
6
5
PSTOP —
—
Initial value :
0
0
0
Read/Write : R/W
R/W
—
H'FF3A
Clock Pulse Generator
4
3
2
1
0
—
—
SCK2 SCK1 SCK0
0
0
0
0
0
—
—
R/W
R/W
R/W
Bus Master Clock Select
0 0 0 Bus master is in high-speed mode
1 Medium-speed clock is ø/2
1 0 Medium-speed clock is ø/4
1 Medium-speed clock is ø/8
1 0 0 Medium-speed clock is ø/16
1 Medium-speed clock is ø/32
1 ——
ø Clock Output Control
PSTOP Normal Operation Sleep Mode
0
ø output
1
Fixed high
ø output
Fixed high
Software
Standby Mode
Fixed high
Fixed high
Hardware
Standby Mode
High impedance
High impedance
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