HD6432345 Datasheet, PDF (188/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

6.7.4 Transition Timing
Figure 6.19 shows the timing for transition to the bus-released state.
ø
Address bus
Data bus
AS
RD
HWR, LWR
CPU cycle
T₀
T₁
T₂
Address
External bus released state
High impedance
High impedance
High impedance
High impedance
High impedance
CPU
cycle
BREQ
BACK
Minimum
1 state
[1]
[2]
[3]
[4]
[5]
[1]
Low level of BREQ pin is sampled at rise of T₂ state.
[2]
BACK pin is driven low at end of CPU read cycle, releasing bus to external
bus master.
[3]
BREQ pin state is still sampled in external bus released state.
[4]
High level of BREQ pin is sampled.
[5]
BACK pin is driven high, ending bus release cycle.
Figure 6.19 Bus-Released State Transition Timing
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