HD6432345 Datasheet, PDF (197/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

7.2.3 DTC Source Address Register (SAR)
Bit
: 23 22 21 20 19
43210
Initial value: Unde- Unde- Unde-Unde- Unde-
fined fined fined fined fined
R/W
: —————
Unde- Unde-Unde- Unde-Unde-
fined fined fined fined fined
—————
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.
For word-size transfer, specify an even source address.
7.2.4 DTC Destination Address Register (DAR)
Bit
: 23 22 21 20 19
43210
Initial value : Unde- Unde- Unde-Unde- Unde-
fined fined fined fined fined
R/W
: —————
Unde- Unde-Unde- Unde-Unde-
fined fined fined fined fined
—————
DAR is a 24-bit register that designates the destination address of data to be transferred by the
DTC. For word-size transfer, specify an even destination address.
7.2.5 DTC Transfer Count Register A (CRA)
Bit
: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: Unde- Unde- Unde-Unde- Unde-Unde- Unde-Unde- Unde-Unde- Unde-Unde- Unde-Unde- Unde-Unde-
fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined
R/W
: ————————————————
CRAH
CRAL
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.
In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is
decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits
(CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL
functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is
transferred, and the contents of CRAH are sent when the count reaches H'00. This operation is
repeated.
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