HD6432345 Datasheet, PDF (160/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a
burst ROM interface burst access.
Bit 3
BRSTS0
0
1
Description
Max. 4 words in burst access
Max. 8 words in burst access
(Initial value)
Bits 2 to 0—Reserved: Only 0 should be written to these bits.
6.2.5 Bus Control Register L (BCRL)
Bit
:
7
6
5
4
3
2
1
0
BRLE
—
EAE
—
—
—
— WAITE
Initial value :
0
0
1
1
1
1
0
0
R/W
:
R/W
R/W R/W
R/W R/W
R/W
R/W R/W
BCRL is an 8-bit readable/writable register that performs selection of the external bus-released
state protocol, and enabling or disabling of WAIT pin input.
BCRL is initialized to H'3C by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset or in software standby mode.
Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release.
Bit 7
BRLE
0
1
Description
External bus release is disabled. BREQ and BACK can be used as I/O ports.
(Initial value)
External bus release is enabled.
Bit 6—Reserved: Only 0 should be written to this bit.
Bit 5—External Address Enable (EAE): Selects whether addresses H'010000 to H'01FFFF are
to be internal addresses or external addresses.
This setting is invalid in normal mode*.
Note: * ZTAT, mask ROM, and ROMless versions only.
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