HD6432345 Datasheet, PDF (36/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Table 1.3 Pin Functions (cont)
Type
Symbol
Operating mode MD₂ to
control
MD₀
System control RES
STBY
BREQ
BACK
FWE*¹
Pin No.
FP-100B,
TFP-100B,
TFP-100G FP-100A
61, 58, 63, 60,
57
59
62
64
64
66
76
78
75
77
60
62
I/O Name and Function
Input
• ZTAT, mask ROM, and ROMless
versions
Operating
MD₂ MD₁ MD₀ Mode
0
0
0
—
1
Mode 1
1
0
Mode 2*
1
Mode 3*
1
0
0
Mode 4
1
Mode 5
1
0
Mode 6*
1
Mode 7*
Note: * Not used on ROMless
version.
Input
Reset input: When this pin is driven
low, the chip is reset. The type of
reset can be selected according to
the NMI input level. At power-on, the
NMI pin input level should be set
high.
Input
Standby: When this pin is driven low,
a transition is made to hardware
standby mode.
Input
Bus request: Used by an external
bus master to issue a bus request to
the H8S/2345 Series.
Output Bus request acknowledge: Indicates
that the bus has been released to an
external bus master.
Input Flash write enable: Enables or
disables writing to flash memory.
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