HD6432345 Datasheet, PDF (382/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Contention between TGR Read and Input Capture: If the input capture signal is generated in
the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer.
Figure 9.53 shows the timing in this case.
ø
Address
Read signal
Input capture
signal
TGR
TGR read cycle
T1
T2
TGR address
X
M
Internal
M
data bus
Figure 9.53 Contention between TGR Read and Input Capture
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