HD6432345 Datasheet, PDF (376/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC is activated, the flag is cleared automatically. Figure 9.46 shows the timing
for status flag clearing by the CPU, and figure 9.47 shows the timing for status flag clearing by the
DTC.
TSR write cycle
T1
T2
ø
Address
TSR address
Write signal
Status flag
Interrupt
request
signal
Figure 9.46 Timing for Status Flag Clearing by CPU
ø
Address
Status flag
DTC
read cycle
T1
T2
DTC
write cycle
T1
T2
Source address
Destination
address
Interrupt
request
signal
Figure 9.47 Timing for Status Flag Clearing by DTC Activation
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