HD6432345 Datasheet, PDF (305/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge.
When the input clock is counted using both edges, the input clock period is halved (e.g. ø/4 both
edges = ø/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is
ignored and the phase counting mode setting has priority.
Bit 4
Bit 3
CKEG1 CKEG0 Description
0
0
Count at rising edge
(Initial value)
1
Count at falling edge
1
—
Count at both edges
Note: Internal clock edge selection is valid when the input clock is ø/4 or slower. This setting is
ignored if the input clock is ø/1, or when overflow/underflow of another channel is selected.
Bits 2, 1, and 0—Time Prescaler 2, 1, and 0 (TPSC2 to TPSC0): These bits select the TCNT
counter clock. The clock source can be selected independently for each channel. Table 9.4 shows
the clock sources that can be set for each channel.
Table 9.4 TPU Clock Sources
Internal Clock
Channel ø/1 ø/4 ø/16 ø/64 ø/256 ø/1024 ø/4096
Overflow/
External Clock
Underflow
on Another
TCLKA TCLKB TCLKC TCLKD Channel
0
1
2
3
4
5
Legend
: Setting
Blank : No setting
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