HD6432345 Datasheet, PDF (576/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Bit 0—Program Setup (PSU): Prepares for a transition to program mode. Set this bit to 1 before
setting the P bit to 1 in FLMCR1. Do not set the SWE, ESU, EV, PV, E, or P bit at the same time.
Bit 0
PSU
0
1
Description
Program setup cleared
Program setup
[Setting condition]
When FWE = 1, and SWE = 1
(Initial value)
17.7.3 Erase Block Registers 1 and 2 (EBR1, EBR2)
Bit
7
6
5
4
3
EBR1
—
—
—
—
—
Initial value 0
0
0
0
0
Read/Write —
—
—
—
—
2
1
0
—
EB9 EB8
0
0
0
—
R/W R/W
Bit
7
6
5
4
3
2
1
0
EBR2
EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0
Initial value 0
0
0
0
0
0
0
0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
EBR1 and EBR2 are registers that specify the flash memory erase area block by block; bits 1 and
2 in EBR1 and bits 7 to 0 in EBR2 are readable/writable bits. EBR1 and EBR2 are each initialized
to H'00 by a reset, in hardware standby mode and software standby mode, when a low level is
input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in FLMCR1
is cleared to 0. When a bit in EBR1 or EBR2 is set, the corresponding block can be erased. Other
blocks are erase-protected. Blocks are erased separately (in one-block units), so set only one bit in
EBR1 or EBR2 (more than one bit cannot be set to 1). To erase all blocks, erase one block at a
time, once after another in sequence. Then on-chip flash memory is disabled (modes 4 and 5), a
read with return H'00, and writes are disabled.
The flash memory block configuration is shown in table 17.12.
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