HD6432345 Datasheet, PDF (485/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

16 clocks
8 clocks
0
7
Internal basic
clock
15 0
7
15 0
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
Start bit
D0
D1
Figure 12.21 Receive Data Sampling Timing in Asynchronous Mode
Thus the reception margin in asynchronous mode is given by formula (1) below.
M = (0.5 – ¹ ) – (L – 0.5) F – ^{D – 0.5} (1 + F) × 100% . . . . . . . . Formula (1)
2N
N
Where M : Reception margin (%)
N : Ratio of bit rate to clock (N = 16)
D : Clock duty (D = 0 to 1.0)
L : Frame length (L = 9 to 12)
F : Absolute value of clock rate deviation
Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin of 46.875% is given by
formula (2) below.
When D = 0.5 and F = 0,
1
M = (0.5 –
) × 100%
2 × 16
= 46.875%
. . . . . . . . Formula (2)
However, this is only the computed value, and a margin of 20% to 30% should be allowed in
system design.
471