HD6432345 Datasheet, PDF (901/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Table D.1 I/O Port States in Each Processing State (cont)
Port Name
Pin Name
MCU
Operating
Mode
Power-
On
Manual
Reset Reset
Hardware Software
Standby Standby
Mode
Mode
Bus
Release
State
PG₃/CS1
1 to 3, 7
T
PG2/CS2
4 to 6
T
PG1/CS3/
IRQ7
kept
T
[DDR = 0] T
T
[DDR = 1]
H*
kept
kept
[DDR · OPE = 0] T
T
[DDR · OPE = 1]
H
PG₀/ADTRG/ 1 to 3, 7
T
kept
T
kept
kept
IRQ6
4 to 6
T
kept
T
kept
T
Legend:
H
L
T
kept
DDR
OPE
WAITE
BRLE
: High level
: Low level
: High impedance
: Input port becomes high-impedance, output port retains state
: Data direction register
: Output port enable
: Wait input enable
: Bus release enable
Note: * Indicates the state after completion of the executing bus cycle.
Program
Execution
State
Sleep Mode
I/O port
[DDR = 0]
Input port
[DDR = 1]
CS₁ to CS₃
I/O port
I/O port
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