HD6432345 Datasheet, PDF (186/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

6.6.2 Pin States in Idle Cycle
Table 6.5 shows pin states in an idle cycle.
Table 6.5 Pin States in Idle Cycle
Pins
A₂₃ to A₀
D₁₅ to D₀
CSn
AS
RD
HWR
LWR
Pin State
Contents of next bus cycle
High impedance
High
High
High
High
High
6.7 Bus Release
6.7.1 Overview
The H8S/2345 Series can release the external bus in response to a bus request from an external
device. In the external bus released state, the internal bus master continues to operate as long as
there is no external access.
6.7.2 Operation
In external expansion mode, the bus can be released to an external device by setting the BRLE bit
in BCRL to 1. Driving the BREQ pin low issues an external bus request to the H8S/2345 Series.
When the BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the
address bus, data bus, and bus control signals are placed in the high-impedance state, establishing
the external bus-released state.
In the external bus released state, an internal bus master can perform accesses using the internal
bus. When an internal bus master wants to make an external access, it temporarily defers
activation of the bus cycle, and waits for the bus request from the external bus master to be
dropped.
When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the
external bus released state is terminated.
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