HD6432345 Datasheet, PDF (770/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

MRB—DTC Mode Register B
H'F800—H'FBFF
DTC
Bit
:
Initial value :
Read/Write :
7
6
5
4
3
2
1
0
CHNE DISEL —
—
—
—
—
—
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
—
—
—
—
—
—
—
—
Reserved
Only 0 should be written to these bits
DTC Interrupt Select
0 After a data transfer ends, the CPU interrupt is
disabled unless the transfer counter is 0
1 After a data transfer ends, the CPU interrupt is enabled
DTC Chain Transfer Enable
0 End of DTC data transfer
1 DTC chain transfer
SAR—DTC Source Address Register
H'F800—H'FBFF
DTC
Bit
: 23 22 21 20 19
---
43210
---
Initial value : Unde- Unde- Unde- Unde- Unde-
---
Unde- Unde- Unde- Unde- Unde-
fined fined fined fined fined
fined fined fined fined fined
Read/Write : — — — — —
---
— — —— —
Specifies transfer data source address
DAR—DTC Destination Address Register
H'F800—H'FBFF
DTC
Bit
: 23 22 21 20 19
---
43210
---
Initial value : ^{Unde- Unde- Unde- Unde- Unde-}
---
Unde- Unde- Unde- Unde- Unde-
fined fined fined fined fined
fined fined fined fined fined
Read/Write : — — — — —
---
—————
Specifies transfer data destination address
761