HD6432345 Datasheet, PDF (9/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

4.2.5 State of On-Chip Supporting Modules after Reset Release ................................. 96
4.3 Traces ................................................................................................................................ 97
4.4 Interrupts............................................................................................................................ 98
4.5 Trap Instruction ................................................................................................................. 99
4.6 Stack Status after Exception Handling .............................................................................. 100
4.7 Notes on Use of the Stack.................................................................................................. 101
Section 5 Interrupt Controller ........................................................................................ 103
5.1 Overview............................................................................................................................ 103
5.1.1 Features ................................................................................................................ 103
5.1.2 Block Diagram...................................................................................................... 104
5.1.3 Pin Configuration ................................................................................................. 105
5.1.4 Register Configuration ......................................................................................... 105
5.2 Register Descriptions......................................................................................................... 106
5.2.1 System Control Register (SYSCR) ..................................................................... 106
5.2.2 Interrupt Priority Registers A to K (IPRA to IPRK) ............................................ 107
5.2.3 IRQ Enable Register (IER) .................................................................................. 108
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 109
5.2.5 IRQ Status Register (ISR) .................................................................................... 110
5.3 Interrupt Sources................................................................................................................ 111
5.3.1 External Interrupts................................................................................................ 111
5.3.2 Internal Interrupts ................................................................................................. 112
5.3.3 Interrupt Exception Handling Vector Table ......................................................... 112
5.4 Interrupt Operation ............................................................................................................ 116
5.4.1 Interrupt Control Modes and Interrupt Operation ................................................ 116
5.4.2 Interrupt Control Mode 0...................................................................................... 119
5.4.3 Interrupt Control Mode 2...................................................................................... 121
5.4.4 Interrupt Exception Handling Sequence .............................................................. 123
5.4.5 Interrupt Response Times..................................................................................... 125
5.5 Usage Notes ....................................................................................................................... 126
5.5.1 Contention between Interrupt Generation and Disabling..................................... 126
5.5.2 Instructions that Disable Interrupts ...................................................................... 127
5.5.3 Times when Interrupts are Disabled..................................................................... 127
5.5.4 Interrupts during Execution of EEPMOV Instruction.......................................... 127
5.6 DTC Activation by Interrupt ............................................................................................. 128
5.6.1 Overview .............................................................................................................. 128
5.6.2 Block Diagram...................................................................................................... 128
5.6.3 Operation .............................................................................................................. 129
Section 6 Bus Controller.................................................................................................. 131
6.1 Overview............................................................................................................................ 131
6.1.1 Features ................................................................................................................ 131
6.1.2 Block Diagram...................................................................................................... 132
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