HD6432345 Datasheet, PDF (577/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Table 17.12 Flash Memory Erase Blocks
Block (Size)
EB0 (1 kbyte)
EB1 (1 kbyte)
EB2 (1 kbyte)
EB3 (1 kbyte)
EB4 (28 kbytes)
EB5 (16 kbytes)
EB6 (8 kbytes)
EB7 (8 kbytes)
EB8 (32 kbytes)
EB9 (32 kbytes)
Address
H'000000 to H'0003FF
H'000400 to H'0007FF
H'000800 to H'000BFF
H'000C00 to H'000FFF
H'001000 to H'007FFF
H'008000 to H'00BFFF
H'00C000 to H'00DFFF
H'00E000 to H'00FFFF
H'010000 to H'017FFF
H'018000 to H'01FFFF
17.7.4 System Control Register 2 (SYSCR2)
Bit
7
6
5
4
3
2
1
0
—
—
—
— FLSHE —
—
—
Initial value 0
0
0
0
0
0
0
0
Read/Write —
—
—
—
R/W
—
—
—
SYSCR2 is an 8-bit readable/writable register that controls on-chip flash memory (in F-ZTAT
versions).
SYSCR2 is initialized to H'00 by a reset and in hardware standby mode.
SYSCR2 is available only in the F-ZTAT version. In the mask ROM and ZTAT versions, this
register cannot be written to and will return an undefined value if read.
Bits 7 to 4—Reserved: Read-only bits, always read as 0.
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash
memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Setting the FLSHE bit to 1
enables read/write access to the flash memory control registers. If FLSHE is cleared to 0, the flash
memory control registers are deselected. In this case, the flash memory control register contents
are retained.
565