HD6432345 Datasheet, PDF (620/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Section 18 Clock Pulse Generator
18.1 Overview
The H8S/2345 Series has a built-in clock pulse generator (CPG) that generates the system clock
(ø), the bus master clock, and internal clocks.
The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, a medium-
speed clock divider, and a bus master clock selection circuit.
18.1.1 Block Diagram
Figure 18.1 shows a block diagram of the clock pulse generator.
EXTAL
XTAL
Oscillator
Duty
adjustment
circuit
SCKCR
SCK2 to SCK0
Medium-
speed
divider
ø/2 to ø/32 Bus master
clock
selection
circuit
System clock to ø pin
Internal clock
to supporting
modules
Bus master clock
to CPU and DTC
Figure 18.1 Block Diagram of Clock Pulse Generator
18.1.2 Register Configuration
The clock pulse generator is controlled by SCKCR. Table 18.1 shows the register configuration.
Table 18.1 Clock Pulse Generator Register
Name
Abbreviation R/W
System clock control register
SCKCR
R/W
Note:* Lower 16 bits of the address.
Initial Value
H'00
Address*
H'FF3A
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