HD6432345 Datasheet, PDF (494/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

13.2.3 Serial Mode Register (SMR)
Bit
:
7
6
5
4
3
2
1
0
GM
CHR
PE
O/E STOP MP CKS1 CKS0
Initial value :
0
0
0
0
0
0
0
0
Set value* :
GM
0
1
O/E
1
0
CKS1 CKS0
R/W
:
R/W
R/W R/W
R/W R/W
R/W
R/W R/W
Note: * When the smart card interface is used, be sure to make the 0 or 1 setting shown for
bits 6, 5, 3, and 2.
Bit 7 of SMR has a different function in smart card interface mode.
Bit 7—GSM Mode (GM): Sets the smart card interface function to GSM mode.
This bit is cleared to 0 when the normal smart card interface is used. In GSM mode, this bit is set
to 1, the timing of setting of the TEND flag that indicates transmission completion is advanced
and clock output control mode addition is performed. The contents of the clock output control
mode addition are specified by bits 1 and 0 of the serial control register (SCR).
Bit 7
GM
Description
0
Normal smart card interface mode operation
(Initial value)
• TEND flag generation 12.5 etu after beginning of start bit
• Clock output ON/OFF control only
1
GSM mode smart card interface mode operation
• TEND flag generation 11.0 etu after beginning of start bit
• High/low fixing control possible in addition to clock output ON/OFF control (set by
SCR)
Note: etu: Elementary time unit (time for transfer of 1 bit)
Bits 6 to 0—Operate in the same way as for the normal SCI.
For details, see section 12.2.5, Serial Mode Register (SMR).
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