HD6432345 Datasheet, PDF (187/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

In the event of simultaneous external bus release request and external access request generation,
the order of priority is as follows:
(High) External bus release > Internal bus master external access (Low)
6.7.3 Pin States in External Bus Released State
Table 6.6 shows pin states in the external bus released state.
Table 6.6 Pin States in Bus Released State
Pins
A₂₃ to A₀
D₁₅ to D₀
CSn
AS
RD
HWR
LWR
Pin State
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
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