HD6432345 Datasheet, PDF (215/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Table 7.9 Number of States Required for Each Execution Status
Object to be Accessed
Bus width
Access states
Execution Vector read
S_I
status
Register
S_J
information
read/write
Byte data read S_K
Word data read S_K
Byte data write S_L
Word data write S_L
Internal operation S_M
On-
Chip
RAM
32
1
—
1
On-
Chip
ROM
16
1
1
—
On-Chip I/O
Registers
8
16
2
2
——
——
External Devices
8
16
2
3
2
4
6+2m 2
———
1
1
2
2
2
3+m 2
1
1
4
2
4
6+2m 2
1
1
2
2
2
3+m 2
1
1
4
2
4
6+2m 2
1
3
3+m
—
3+m
3+m
3+m
3+m
The number of execution states is calculated from the formula below. Note that Σ means the sum
of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,
plus 1).
Number of execution states = I · S_I + Σ (J · S_J + K · S_K + L · S_L) + M · S_M
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from the on-chip ROM to an internal I/O register, the time required for the
DTC operation is 13 states. The time from activation to the end of the data write is 10 states.
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