HD6432345 Datasheet, PDF (275/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Port D MOS Pull-Up Control Register (PDPCR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port D on an individual bit basis.
When a PDDDR bit is cleared to 0 (input port setting) in mode 3 or 7, setting the corresponding
PDPCR bit to 1 turns on the MOS input pull-up for the corresponding pin.
PDPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state after a manual reset, and in software standby mode.
8.9.3 Pin Functions
Modes 1, 2, 4, 5, and 6*: In modes 1, 2, 4, 5, and 6*, port D pins are automatically designated as
data I/O pins.
Port D pin functions in modes 1, 2, 4, 5, and 6 are shown in figure 8.18.
Port D
D₁₅ (I/O)
D₁₄ (I/O)
D₁₃ (I/O)
D₁₂ (I/O)
D₁₁ (I/O)
D₁₀ (I/O)
D₉ (I/O)
D₈ (I/O)
Figure 8.18 Port D Pin Functions (Modes 1, 2, 4, 5, and 6)*
Modes 3 and 7*: In modes 3 and 7*, port D pins function as I/O ports. Input or output can be
specified for each pin on an individual bit basis. Setting a PDDDR bit to 1 makes the
corresponding port D pin an output port, while clearing the bit to 0 makes the pin an input port.
Note: * Modes 1 to 3 are not available on the F-ZTAT version.
Modes 2, 3, 6, and 7 are not available on the ROMless version.
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