HD6432345 Datasheet, PDF (419/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

11.3 Operation
11.3.1 Watchdog Timer Operation
To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1. Software must prevent
TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows
occurs. This ensures that TCNT does not overflow while the system is operating normally. If
TCNT overflows without being rewritten because of a system crash or other error, the WDTOVF
signal* is output. This is shown in figure 11.4. This WDTOVF signal* can be used to reset the
system. The WDTOVF signal* is output for 132 states when RSTE = 1, and for 130 states when
RSTE = 0.
If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, a signal that resets the H8S/2345
Series internally is generated at the same time as the WDTOVF signal*. This reset can be selected
as a power-on reset or a manual reset, depending on the setting of the RSTS bit in RSTCSR. The
internal reset signal is output for 518 states.
If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a
WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0.
Note: * The WDTOVF pin function is not supported by the F-ZTAT version.
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