HD6432345 Datasheet, PDF (819/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

SMR0—Serial Mode Register 0
H'FF78
Smart Card Interface 0
Bit
:
7
6
5
4
3
2
1
0
GM
CHR
PE
O/E STOP MP CKS1 CKS0
Initial value :
0
0
0
0
0
0
0
0
Read/Write : R/W
R/W
R/W
R/W R/W
R/W
R/W
R/W
Clock Select
0 0 ø clock
1 ø/4 clock
1 0 ø/16 clock
1 ø/64 clock
Multiprocessor Mode
0 Multiprocessor function disabled
1 Setting prohibited
Stop Bit Length
0 Setting prohibited
1 2 stop bits
Parity Mode
0 Even parity
1 Odd parity
Parity Enable
0 Setting prohibited
1 Parity bit addition and checking enabled
Character Length
0 8-bit data
GSM Mode
1 Setting prohibited
0 Normal smart card interface mode operation
• TEND flag generated 12.5 etu after beginning of start bit
• Clock output on/off control only
1 GSM mode smart card interface mode operation
• TEND flag generated 11.0 etu after beginning of start bit
• Fixed high/low-level control possible (set in SCR) in addition to clock output on/off control
Note: etu (Elementary Time Unit): Interval for transfer of one bit
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