HD6432345 Datasheet, PDF (136/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Figure 5.4 shows a block diagram of the priority decision circuit.
Interrupt
control
mode 0 I
Interrupt source
Interrupt
acceptance
control
8-level
mask control
Default priority
determination
Vector number
I2 to I0
IPR
Interrupt control mode 2
Figure 5.4 Block Diagram of Interrupt Control Operation
(1) Interrupt Acceptance Control
In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR.
Table 5.6 shows the interrupts selected in each interrupt control mode.
Table 5.6 Interrupts Selected in Each Interrupt Control Mode (1)
Interrupt Control Mode
0
2
Legend
* : Don't care
Interrupt Mask Bits
I
0
1
*
Selected Interrupts
All interrupts
NMI interrupts
All interrupts
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