HD6432345 Datasheet, PDF (654/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Table 20.7 Timing of On-Chip Supporting Modules (cont)
Condition A: —In planning stage—
V_CC = AV_CC = 3.0 V to 5.5 V, V_ref = 3.0 V to AV_CC, V_SS = AV_SS = 0 V,
ø = 2 to 10 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Condition B: V_CC = AV_CC = 5.0 V ± 10%, V_ref = 4.5 V to AV_CC, V_SS = AV_SS = 0 V,
ø = 2 to 20 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Item
Symbol
SCI
Input Asynchro- t_Scyc
clock nous
cycle _Synchro-
nous
Input clock pulse
width
t _SCKW
Input clock rise
t _SCKr
time
Input clock fall
t _SCKf
time
Transmit data
t _TXD
delay time
Receive data setup t_RXS
time (synchronous)
Receive data hold t_RXH
time (synchronous)
A/D
Trigger input setup t_TRGS
converter time
Condition A
Min Max
4
—
6
—
0.4 0.6
— 1.5
— 1.5
— 100
100 —
100 —
50 —
Condition B
Min Max Unit
4
—
t _cyc
6
—
0.4 0.6
t _Scyc
—
1.5
t _cyc
— 1.5
— 50
ns
50 —
ns
50 —
ns
30 —
ns
Test Conditions
Figure 20.24
Figure 20.25
Figure 20.26
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