HD6432345 Datasheet, PDF (652/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Table 20.6 Bus Timing (cont)
Condition A: —In planning stage—
V_CC = AV_CC = 3.0 to 5.5 V, V_ref = 3.0 V to AV_CC, V_SS = AV_SS = 0 V,
ø = 2 to 10 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Condition B: V_CC = AV_CC = 5.0 V ± 10%, V_ref = 4.5 V to AV_CC, V_SS = AV_SS = 0 V,
ø= 2 to 20 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Item
WR delay time 1
WR delay time 2
WR pulse width 1
Symbol
t _WRD1
t _WRD2
t _WSW1
WR pulse width 2
t _WSW2
Write data delay time t_WDD
Write data setup time t_WDS
Write data hold time t_WDH
WAIT setup time
WAIT hold time
BREQ setup time
BACK delay time
Bus-floating time
t _WTS
t _WTH
t _BRQS
t _BACD
t _BZD
Condition A
Min Max
—
40
—
40
1.0 × —
t_cyc – 40
1.5 × —
t_cyc – 40
—
60
0.5 × —
t_cyc – 40
0.5 × —
t_cyc – 20
60
—
10
—
60
—
—
30
—
100
Condition B
Min Max
—
20
—
20
1.0 × —
t_cyc – 20
1.5 × —
t_cyc – 20
—
30
0.5 × —
t_cyc – 20
0.5 × —
t_cyc – 10
30
—
5
—
30
—
—
15
—
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions
Figure 20.11 to
Figure 20.15
Figure 20.13
Figure 20.16
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