HD6432345 Datasheet, PDF (799/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

BCRL—Bus Control Register L
H'FED5
Bus Controller
Bit
:
7
6
5
4
3
2
1
0
BRLE
—
EAE
—
—
—
— WAITE
Initial value :
0
0
1
1
1
1
0
0
Read/Write : R/W
R/W R/W
R/W R/W R/W
R/W R/W
Reserved
Only 0 should be written to this bit
WAIT Pin Enable
0 Wait input by WAIT pin disabled
1 Wait input by WAIT pin enabled
Reserved
Only 1 should be written to these bits
External Addresses H'010000 to H'01FFFF Enable
0 On-chip ROM (H8S/2345) or reserved area* (H8S/2343)
1 External addresses (in external expansion mode) or
reserved area (in single-chip mode)
Note: * Do not access a reserved area.
Reserved
Only 0 should be written to this bit
Bus Release Enable
0 External bus release is disabled
1 External bus release is enabled
790