HD6432345 Datasheet, PDF (513/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

372 clocks
186 clocks
0
185
371 0
Internal
basic
clock
Receive
data (RxD)
Start bit
D0
185
371 0
D1
Synchro-
nization
sampling
timing
Data
sampling
timing
Figure 13.10 Receive Data Sampling Timing in Smart Card Mode
Thus the reception margin in smart card interface mode is given by the following formula.
M = (0.5 – ¹ ) – (L – 0.5) F – ^{D – 0.5} (1 + F) × 100%
2N
N
Where M: Reception margin (%)
N: Ratio of bit rate to clock (N = 372)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
Assuming values of F = 0 and D = 0.5 in the above formula, the reception margin formula is as
follows.
When D = 0.5 and F = 0,
M = (0.5 – 1/2 × 372) × 100%
= 49.866%
499