HD6432345 Datasheet, PDF (112/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

4.1.2 Exception Handling Operation
Exceptions originate from various sources. Trap instructions and interrupts are handled as
follows:
1. The program counter (PC), condition code register (CCR), and extended register (EXR) are
pushed onto the stack.
2. The interrupt mask bits are updated. The T bit is cleared to 0.
3. A vector address corresponding to the exception source is generated, and program execution
starts from that address.
For a reset exception, steps 2 and 3 above are carried out.
4.1.3 Exception Vector Table
The exception sources are classified as shown in figure 4.1. Different vector addresses are
assigned to different exception sources.
Table 4.2 lists the exception sources and their vector addresses.
Exception
sources
Reset
Trace
Interrupts
Power-on reset
Manual reset
External interrupts: NMI, IRQ7 to IRQ0
Internal interrupts: 43 interrupt sources in
on-chip supporting modules
Trap instruction
Figure 4.1 Exception Sources
In modes 6 and 7 in the H8S/2345, the on-chip ROM available for use after a power-on reset is the
64-kbyte area comprising addresses H'000000 to H'00FFFF. Care is required when setting vector
addresses. In this case, clearing the EAE bit in BCRL enables the 128-kbyte area comprising
addresses H'000000 to H'01FFFF to be used.
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