HD6432345 Datasheet, PDF (42/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

• High-speed operation
 All frequently-used instructions execute in one or two states
 Maximum clock rate
: 20 MHz
 8/16/32-bit register-register add/subtract : 50 ns
 8 × 8-bit register-register multiply
: 600 ns
 16 ÷ 8-bit register-register divide
: 600 ns
 16 × 16-bit register-register multiply : 1000 ns
 32 ÷ 16-bit register-register divide
: 1000 ns
• Two CPU operating modes
 Normal mode (Supported on ZTAT, mask ROM, and ROMless versions only)
 Advanced mode
• Power-down state
 Transition to power-down state by SLEEP instruction
 CPU clock speed selection
2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
• Register configuration
The MAC register is supported only by the H8S/2600 CPU.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.
• Number of execution states
The number of execution states of the MULXU and MULXS instructions.
Instruction
MULXU
MULXS
Mnemonic
MULXU.B Rs, Rd
MULXU.W Rs, ERd
MULXS.B Rs, Rd
MULXS.W Rs, ERd
H8S/2600
3
4
4
5
Internal Operation
H8S/2000
12
20
13
21
There are also differences in the address space, CCR and EXR register functions, power-down
state, etc., depending on the product.
22