HD6432345 Datasheet, PDF (255/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

8.6.2 Register Configuration
Table 8.9 shows the port A register configuration.
Table 8.9 Port A Registers
Name
Abbreviation R/W
Port A data direction register
PADDR
W
Port A data register
PADR
R/W
Port A register
PORTA
R
Port A MOS pull-up control register PAPCR
R/W
Port A open-drain control register PAODR
R/W
Notes: 1. Value of bits 3 to 0.
2. Lower 16 bits of the address.
Initial Value*¹
H'0
H'0
Undefined
H'0
H'0
Address*²
H'FEB9
H'FF69
H'FF59
H'FF70
H'FF77
Port A Data Direction Register (PADDR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
—
—
—
— PA3DDR PA2DDR PA1DDR PA0DDR
Undefined Undefined Undefined Undefined 0
0
0
0
—
—
—
—
W
W
W
W
PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port A. PADDR cannot be read; if it is, an undefined value will be read. Bits 7 to 4 are
reserved.
PADDR is initialized to H'0 (bits 3 to 0) by a power-on reset and in hardware standby mode. It
retains its prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR
is used to select whether the address output pins retain their output state or become high-
impedance when a transition is made to software standby mode.
• Modes 1, 2, 3, and 7*
Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing
the bit to 0 makes the pin an input port.
• Modes 4 and 5
The corresponding port A pins are address outputs irrespective of the value of bits PA3DDR to
PA0DDR.
Note: * Modes 1 to 3 are not available on the F-ZTAT version.
Modes 2, 3, 6, and 7 are not available on the ROMless version.
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